MCHPC'19: Workshop on Memory Centric High Performance Computing

Location: Room 501, Colorado Convention Center, Denver Colorado USA

Time/Date: 9:00AM - 5:30PM, Monday, November 18, 2019

held in conjunction with SC19: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with IEEE TCHPC

SC19      tchpc

Introduction      CFP     Organizers      Program Committee      Submission      Program      Previous Workshops


The growing disparity between CPU speed and memory speed, known as the memory wall problem, has been one of the most critical and long-standing challenges in the computing industry. The situation is further complicated by the recent expansion of the memory hierarchy, which is becoming deeper and more diversified with the adoption of new memory technologies and architectures including 3D-stacked memory, non-volatile random-access memory (NVRAM), memristor, hybrid software and hardware caches, etc. Computer architecture and hardware system, operating systems, storage and file systems, programming stack, performance model and tools are being enhanced, augmented, or even redesigned to address the performance, programmability and energy efficiency challenges of the increasingly complex and heterogeneous memory systems for HPC and data-intensive applications.

The MCHPC workshop aims to bring together computer and computational science researchers, from industry, government labs and academia, concerned with the challenges of efficiently using existing and emerging memory systems for high performance computing. The term performance for memory system is general, which include latency, bandwidth, power consumption and reliability from the aspect of hardware memory technologies to what it is manifested in the application performance. The topics of interest for the MCHPC workshop include, but are not limited to:

Important Dates


Program Committee


Authors are invited to submit manuscripts in English structured as technical papers up to 8 pages or as short papers up to 5 pages, both of letter size (8.5in x 11in) and including figures, tables, and references. Submissions not conforming to these guidelines may be returned without review. Your paper should be formatted using IEEE conference format which can be found from The workshop also encourage submitters to include reproducibility information, using reproducibility initiatives for SC'19 Technical Papers as a guide.

All manuscripts will be peer-reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.

Papers should be submitted electronically at:, choose "SC19 Workshop: MCHPC’19: Workshop on Memory Centric High Performance Computing".

The final papers were accepted to be published through IEEE TCHPC. Published proceedings will be included in the IEEE Xplore digital library. We plan to invite selected papers for an extended version in a journal special issue.


     Program Also Available from SC19 Website, Full Proceedings, (pdf)

09:00 AM - 9:02 AM Welcome, MCHPC'19 Organizers

09:02 AM - 10:00 AM Session 1: Morning Keynote, Prospects for Memory, J. Thomas Pawlowski, presentation

Session Chair: Ron Brightwell

Abstract: The outlook for memory components and systems is at the all-time height of excitement. This talk examines the path we have traversed and the likely future directions we must pursue. We will examine scaling across many parameters, "walls" of all sorts concluding with the one that has emerged as the true wall, the dynamics of heterogeneity in systems and their comprising memories, the need for abstraction (still unsatisfied), options available for processing in or nearer to memory, and the imperative technology redirection that is required to make significant strides forward. Time permitting, a lively question and answer period is anticipated.

Brief Bio: J. Thomas Pawlowski is a systems architect and multi-discipline design engineer currently self-employed as a consultant and entrepreneur. He has recently retired from Micron Technology, Inc. where he was employed for 27 years, holding titles including Senior Director, Fellow, Chief Architect and Chief Technologist. He was at the center of numerous new memory architectures, technologies and concepts including synchronous pipelined burst memory, zero bus turnaround memory, double data rate memory, quad data rate memory, reduced latency memory, SerDes memory, multi-channel memory, 3D memory, abstracted memory, smart memory, non-deterministic finite automata (processing in memory technology), processing in interbank memory regions, processing in memory controllers, processing in NAND memory, processing in 3D memory stacks, memory controllers, 3DXpoint memory management, and cryogenic memory among others. Prior to Micron he served for almost 10 years at Allied-Signal Aerspace/Garrett Canada (now Honeywell). In his colorful career Thomas has many design firsts including first FPGAs, microcontrollers and custom microprocessors in aerospace applications, one of the early laptop computer designs (with perhaps the world's first SSD comprising NOR Flash), a novel electronic musical instrument, a line of high-end loudspeakers, and a from-scratch 2-seat electric vehicle design achieving nearly 400mpge efficiency. Thomas holds a BASc degree in electrical engineering from the University of Waterloo and is an IEEE Fellow. Thomas is available for consulting opportunities and would consider employment offers too good to refuse.

10:00 AM - 10:30 AM Break

10:30 AM - 11:30 AM Session 2: Paper Presentation: Emerging Memory and Architectures

Session Chair: Yonghong Yan

11:30 AM - 12:30 PM Session 3: Paper Presentation: Application and Performance Optimization

Session Chair: Alice Koniges

12:30 PM - 2:00 PM Lunch Break

2:00PM - 3:00 PM Session 4: Paper Presentation: Unified and Heterogeneous Memory

Session Chair: Dong Li

3:00 PM - 3:30 PM Break

3:30 PM – 4:15 PM Session 5: Paper Presentation: Converging Storage and Memory

Session Chair: Xian-He Sun

4:15 PM – 5:30 PM Session 6: Panel, Software and Hardware Support for Programming Heterogeneous Memory

Usability and programmability of complex and heterogeneous memory systems remain significant challenges facing the HPC and data analytics communities. Existing memory systems that include DRAM, SRAM, discrete memory, software unified memory, and distributed memory are difficult to exploit while maintaining portable performance. Approaches include programming language constructs and runtime libraries, OS enhancements, and even hardware mechanisms to enable the competing goals of programmability and portability.

The panel will address challenges and solutions for problems of maintaining portability in applications that must navigate the complex memory hierarchy without sacrificing performance and capability.

   Moderator: Maya B Gokhale (Lawrence Livermore National Laboratory)


  1. Paolo Faraboschi (HPE), Paolo Faraboschi is HPE Fellow and VP. He leads research in the Systems Research Lab at HP Labs. His technical interests lie at the intersection of hardware and software and include low power servers and systems-on-a-chip, workload-optimized, highly-parallel and distributed systems, ILP and VLIW processor architectures, compilers, and embedded systems. presentation

  2. Jeffrey Vetter (ORNL), Jeffrey S. Vetter, Ph.D., is a Distinguished R&D Staff Member, and the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. Vetter also holds a joint appointment at the Electrical Engineering and Computer Science Department of the University of Tennessee-Knoxville. From 2005 through 2015, Vetter held a Joint position at Georgia Institute of Technology, where, from 2009 to 2015, he was the Principal Investigator of the NSF Track 2D Experimental Computing XSEDE Facility, named Keeneland, for large scale heterogeneous computing using graphics processors, and the Director of the NVIDIA CUDA Center of Excellence. presentation

  3. Mike Lang (LANL), Mike Lang has been in HPC at Los Alamos National Labs for 20 years; his research has spanned system performance, systems software, interconnects, and memory. He is currently a LANL Program manager for ASC’s Computational Systems and Software Environments (CSSE) and Advanced Technology Development and Mitigation (ATDM). presentation

  4. David Beckingsale (LLNL), David Beckingsale is a computer scientist in the Center for Applied Scientific Computing (CASC) at Lawrence Livermore National Laboratory. His work focuses on portable programming abstractions, and he is project lead for the Umpire memory management library, and also works on the RAJA a C++ portable programming framework. presentation

  5. Vivek Sarkar (Georgia Tech), Vivek Sarkar is a Professor and the Stephen Fleming Chair for Telecommunications in the College of Computing at at Georgia Tech. He conducts research in programming models, compilers, runtimes, and debuggers for current and future HPC systems. Prior to Georgia Tech, he was at Rice University where he created the Habanero Extreme Scale Software Research Lab and served as department chair, and earlier at IBM, where he worked on the PTRAN, ASTI, Jikes RVM, PERCS and X10 projects. Vivek is an ACM Fellow and has served on ASCAC since 2009, and on CRA’s Board of Directors since 2015. presentation

5:30 PM Closing

Previous Workshops