MCHPC'18: Workshop on Memory Centric High Performance Computing

held in conjunction with SC18: The International Conference on High Performance Computing, Networking, Storage and Analysis

Location: Kay Bailey Hutchison Convention Center, Dallas, TX USA

Time/Date: 9:00AM - 5:30PM, Sunday, November 11, 2018

Introduction      CFP     Organizers      Program Committee      Submission      Program      Previous Workshops


The growing disparity between CPU speed and memory speed, known as the memory wall problem, has been one of the most critical and long-standing challenges in the computing industry. The situation is further complicated by the recent expansion of the memory hierarchy, which is becoming deeper and more diversified with the adoption of new memory technologies and architectures including 3D-stacked memory, non-volatile random-access memory (NVRAM), memristor, hybrid software and hardware caches, etc. Computer architecture and hardware system, operating systems, storage and file systems, programming stack, performance model and tools are being enhanced, augmented, or even redesigned to address the performance, programmability and energy efficiency challenges of the increasingly complex and heterogeneous memory systems for HPC and data-intensive applications.

The MCHPC workshop aims to bring together computer and computational science researchers, from industry, government labs and academia, concerned with the challenges of efficiently using existing and emerging memory systems for high performance computing. The term performance for memory system is general, which include latency, bandwidth, power consumption and reliability from the aspect of hardware memory technologies to what it is manifested in the application performance. The topics of interest for the MCHPC workshop include, but are not limited to:

Important Dates


Program Committee


Authors are invited to submit manuscripts in English structured as technical papers up to 8 pages or as short papers up to 5 pages, both of letter size (8.5in x 11in) and including figures, tables, and references. Submissions not conforming to these guidelines may be returned without review. Your paper should be formatted using sigconf of the ACM Master Article Template from The workshop also encourage submitters to include reproducibility information, using reproducibility initiatives for SC17 Technical Papers as a guide.

All manuscripts will be reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.

Papers should be submitted electronically at: using the "SC18 Workshop: MCHPC18" form.

We are working on proceeding details and the tentative plan is to invite papers presented at the workshop for an expanded version for consideration in a journal special issue.


09:00 AM Welcome, MCHPC'18 Organizers

09:00 AM - 10:00 AM Session 1: Morning Keynote, Converging Storage and Memory, Frank T. Hady (Intel)

Session Chair: TBD

10:00 AM - 10:30 AM Break

10:30 AM - 11:30 AM Session 2: Paper Presentation

Session Chair: TBD

11:30 AM - 12:30 PM Session 3: Paper Presentation

Session Chair: TBD

12:30 PM - 2:00 PM Lunch Break

2:00 PM – 3:00 PM Session 4: Afternoon Keynote, Title TBD, Bruce Jacob (University of Maryland at College Park)

Session Chair: TBD

3:00 PM - 3:30 PM Break

3:30 PM – 4:30 PM Session 5: Paper Presentation

Session Chair: TBD

4:30 PM – 5:30 PM Session 6: Panel, Topic TBD

     Moderator: Maya B Gokhale (Lawrence Livermore National Laboratory)


  1. Mike Ignatowski, Sr. Fellow – Advanced Memory and Reconfigurable Computing - AMD Research
  2. Jonathan C. Beard, Staff Research Engineer - ARM HPC | Future Memory/Compute Systems
  3. TBA
  4. TBA
  5. TBA

5:30 PM Closing

Welcome Remarks, MCHPC'18 Organizers

Session 1: Morning Keynote, Converging Storage and Memory, Frank Hady (Intel)

     Session Chair: TBD


Order of magnitude advances in non-volatile memory density and performance are upon us bringing significant systems level architecture opportunities. The NAND Memory transition to 3D and the introduction of QLC have recently increased NAND SSD storage density at a very rapid pace. Products featuring one terabit per die are available from Intel® Corporation allowing dense storage, for example one PByte in 1U. This large improvement in density brings great value to systems, but also increases the performance/capacity/cost gap between DRAM and storage within the long evolving memory and storage hierarchy. Intel® 3D XPoint™ Memory, with much higher performance than NAND and greater density than DRAM has entered the platform to address this gap - first as SSDs. These Intel® Optane™ SSDs are in use within client and data center platforms as both fast storage volumes and as paged extensions to system memory delivering significant application performance improvements. With low latency and fine grained addressability, this new memory can be accessed as Persistent Memory (PM), avoiding the 4kByte block size and multiple microsecond storage stack that accompany system storage. This Intel® Optane Data Center Persistent Memory is made possible through a series of hardware and software advances. The resulting high capacity, high performance, persistent memory creates opportunities for rethinking algorithms to deliver much higher performance applications. This presentation will explain these new memory technologies, explore their impact on the computing system at the architecture and solution level, and suggest areas of platform exploration relevant to the HPC community.

Speaker: Frank T. Hady (Intel)

Frank T. Hady is an Intel Fellow and the Chief Systems Architect in Intel’s Non-Volatile Memory Solutions Group (NSG). Frank leads architectural definition of products based on both Intel® 3D XPoint™ memory and NAND memory, and guides research into future advances for these products. Frank led the definition of the first Intel Optane products. Frank maintains a platform focus, partnering with others at Intel to define the deep integration of Intel® Optane™ technology into the computing system’s hardware and software. Previously he was Intel’s lead platform I/O architect, delivered research foundational to Intel’s QuickAssist Technology, and delivered significant networking performance advances. Frank has authored or co-authored more than 30 published papers on topics related to networking, storage, and I/O innovation. He holds more than 30 U.S. patents. Frank received his bachelor’s and master’s degrees in electrical engineering from the University of Virginia, and his Ph.D. in electrical engineering from the University of Maryland.

Session 2: Paper Presentations

     Session Chair: TBD

Session 3: Afternoon Keynote, Title TBD, Bruce Jacob (University of Maryland at College Park)

     Session Chair: TBD


Speaker: Bruce Jacob (University of Maryland at College Park)

Session 4: Paper Presentations

     Session Chair: TBD

Session 5: Panel, Topic TBD

Previous Workshops