MCHPC'20: Workshop on Memory Centric High Performance Computing

Time/Date: 10:00AM - 6:30PM, U.S. Eastern Standard Time, Wednesday, November 11, 2020

Virtual Event Info from SC'20

held in conjunction with SC20: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with IEEE TCHPC

SC29      tchpc

Introduction      CFP     Organizers      Program Committee      Submission      Program      Previous Workshops


The growing disparity between CPU speed and memory speed, known as the memory wall problem, has been one of the most critical and long-standing challenges in the computing industry. The situation is further complicated by the recent expansion of the memory hierarchy, which is becoming deeper and more diversified with the adoption of new memory technologies and architectures including 3D-stacked memory, non-volatile random-access memory (NVRAM), memristor, hybrid software and hardware caches, etc. Computer architecture and hardware system, operating systems, storage and file systems, programming stack, performance model and tools are being enhanced, augmented, or even redesigned to address the performance, programmability and energy efficiency challenges of the increasingly complex and heterogeneous memory systems for HPC and data-intensive applications.

The MCHPC workshop aims to bring together computer and computational science researchers, from industry, government labs and academia, concerned with the challenges of efficiently using existing and emerging memory systems for high performance computing. The term performance for memory system is general, which include latency, bandwidth, power consumption and reliability from the aspect of hardware memory technologies to what it is manifested in the application performance. The topics of interest for the MCHPC workshop include, but are not limited to:

Important Dates


Program Committee


Authors are invited to submit manuscripts in English structured as technical papers up to 8 pages or as short papers up to 5 pages, both of letter size (8.5in x 11in) and including figures, tables, and references. Submissions not conforming to these guidelines may be returned without review. Your paper should be formatted using IEEE conference format which can be found from The workshop also encourage submitters to include transparency and reproducibility information, using Transparency and Reproducibility Initiative for SC'20 Technical Papers as guideline.

All manuscripts will be peer-reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.

Papers should be submitted electronically at:, choose "SC20 Workshop: MCHPC'20: Workshop on Memory Centric High Performance Computing".

The final papers are planned to be published through IEEE TCHPC. Published proceedings will be included in the IEEE Xplore digital library.


We appreciate you fill in the online evaluation form for the workshop to give feedback. In the form, you need to select the MCHPC workshop from a drop down list to indicate which workshop your feedback applies to.

10:00am - 10:05am Welcome, by Yonghong Yan, Ron Brightwell, Maya B. Gokhale and Xian-He Sun

10:05am - 11:05am Keynote: The 3rd Wall and the Need for Innovation in Architectures, by Peter Kogge

Session Chair: Maya B. Gokhale

Abstract: In the past we have seen two major "walls" (memory and power) whose vanquishing required significant advances in architecture. This talk will discuss evidence on the emergence of a new third wall dealing with data locality, which is prevalent in data intensive applications where computation is dominated by memory access & movement – not flops, Such apps exhibit large sets of often persistent data, with little reuse during computation, no predictable regularity, significantly different scaling characteristics, and where streaming is becoming important. Solving such problems will take a new set of innovations in architecture to overcome. In addition to data on the new wall, the talk will introduce one possible technique: the concept of migrating threads, and give evidence of its potential value based on several benchmarks that have shown to have scaling difficulties on conventional architectures..

Brief Bio: PETER M. KOGGE is the McCourtney Professor of Computer Science and Engineering at the University of Notre Dame, a retired IBM Fellow, and a founder of Emu Solutions, Inc. His research interests are in massively parallel computing paradigms for unconventional applications. He holds over 40 patents and is author of two books. Prior projects included the IOP - the world’s second multi-threaded parallel processor which flew on every Space Shuttle, EXECUBE - the world's first multi-core processor and first processor on a DRAM chip. His startup, Emu Solutions, has demonstrated the first scalable system that utilizes mobile threads to attack large-scale big data and big graph problems. In 2008, he led DARPA’s Exascale technology study group, which resulted in a widely referenced report on exascale computing. Dr. Kogge has received the Daniel Slotnick best paper award (1994), the IEEE/ACM Seymour Cray award (2012), the IEEE Charles Babbage award (2014), the IEEE Computer Pioneer award (2015), and the Gauss best paper award (2015).

11:05am - 11:30am Break

11:30am - 1:30pm Paper Presentation, Session I - Exploiting Heterogeneous Memory

Session Chair: Ron Brightwell

1:30pm - 2:30pm MCHPC'20 Break

2:30pm - 2:31pm Paper Presentation, Session II - Cache Impacts and Optimizations

Session Chair: Kyle Hale

4:00pm - 4:10pm Closing Remarks by Yonghong Yan

Previous Workshops