You should be able to answer questions or solve problems related to the following topics:
Three major classes of instructions in most RISC-V ISA: Arithmetic-logic instructions, Memory load/store instructions, and control transfer instructions.
add, sub, addi, sll, slli, srl, srli, or, ori, and, andi and xori ) all have three operands, two of which are source operands, named rs1 and rs2 (or immediate for I-type instructions) and one is destination operand named rd. lw and sw, ld and sd for example). These instructions have three operands. The format for load is lw rd, offset(rs1) and the format for store is sw rs2, offset(rs1). There is no rs2 operand for load and there is no destination operand (rd) for store. Know that the effective address (EA), the address to access the memory for load/store instruction, is calcuated by the processor by adding up the number in register rs1 and the offset. Know access memory requires two pieces of information, memory address and data size. Data size is represented by instruction mnemonics (e.g. ld for doubleword, and sw for word). For high-level language, data size is represented by the variable data type (e.g. int for a word, double int for a double word, char for byte, and short for half-word). bne, beq, blt, and bge). The format of those instructions is beq rs1, rs2, L1
and label L is the symbol that point to an instruction. A label is actually the memory address for the instruction the symbol points to.Familar with converting core high-level language expressions or statements in C style to instruction sequence: 1) expressions that use +, -, ||, && operators in C; 2) if-else, for and while loop statements; 3) expressions that have array references (e.g. A[4], B[i]) and know how to convert array reference B[i] to instruction sequences that has load or store instructions; 4) the combination of the above three kinds of statements or expressions.